Control of the timing is critical for a latching sense amplifier (amp is a shorten version of the word amplifier and shall be used throughout) in a memory such as a SRAM (static random access memory). For instance, if the sense am is latched too soon, a wrong output can result. If it is delayed more than necessary, the extra delay is added to the access time of the memory. In a dynamic random access memory (DRAM) a clock is used to control the sense amp timing. However, in asynchronous SRAMs, the problem is more difficult. Schuster et al. use a signal created by any word line changing to a logic high voltage to control sense amp timing. See Schuster, S., et al., "A 20 ns 64k NMOS RAM", ISSCC Digest of Technical Papers, p. 226-227; Feb., 1984. Also see Schuster, S., et al., "An 11 ns 64k (4k.times.16) NMOS RAM," 1985 International Symposium of VLSI Technology, Systems and Applications, p. 24-28; May 1985.
FIG. 1 is a schematic drawing of circuitry representing the Schuster timing approach. Word line drivers comprising inverters 2 are each connected to a respective word line WL. Each word line is connected to the gates of pass transistors (not shown) which are connected between bit lines (BL and BL.sub.--) and memory cells 4. Precharge circuitry 6 is connected to bit lines BL and BL.sub.-- which are in turn connected to pass transistors 8. Pass transistors 8, when turned on, connect memory cells 4 to sense amp 10. N-channel pull down transistors 12 each have a gate connected to a respective word line WL. The drains of transistors 12 are connected by line L to the drain of p-channel pull up transistor 14 which has its source connected to a predetermined voltage Vdd. The drains of transistors 12 and 14 are also connected by line L to the input of inverter 16 which is connected to sense amp 10.
In operation, the circuit of FIG. 1 receives a logic low signal at a selected inverter 2 of a word line driver. This signal is eventually received by the gate of a selected transistor 12 which pulls line L down in voltage. This low voltage is received by the input of inverter 16 which in turn latches sense amp 10 such that the memory state of a selected cell can be determined.
The problem with Schuster's scheme is that the sense amp timing control is based on a dynamic NOR with a relatively large number of inputs. Thus, if Schuster's scheme were employed in a device exposed to, for instance, gamma dot radiation, there would likely be disastorous consequences. Gamma dot radiation is high short pulsed transient dose radiation which creates electron-hole pairs which produces photo current in a memory. Therefore, exposure to gamma dot radiation of a memory employing Schuster's scheme would produce photo current in pull down transistors 12 and cause sense amp 10 to possibly latch at the wrong time. Neither dynamic gates nor a large gate fan-in are good for gamma dot situations. Also, gates with large fan-in are more sensitive to parameter variation.
A need exists for control of sense amplifier latch timing which is not substantially susceptible to transient dose radiation.